[ad_1]
AMD Epyc Genoa with 12 chiplets pictured
Simply yesterday the primary photograph of the brand new SP5 (LGA6096) socket has emerged and now we lastly get to see the next-gen EPYC processor with out the built-in heatspreader.
A Chiphell discussion board member “zhangzhonghao” seems to be the primary particular person to disclose the actual image of the upcoming Zen4 server processor, codenamed Genoa. It’s the first {photograph} exhibiting all 12 chiplets put in on the SP5 package deal.
AMD EPYC “Genoa” CPU, Supply: Chiphell
EPYC Genoa function as much as 96 cores and 192 threads in its full configuration. AMD will launch many SKUs with partially disabled cores, so simply because this processor has 12 chiplets it doesn’t imply it’ll have all 96 cores lively.
Every Zen4 CCD die has an space of 72 mm², which is 8 mm² smaller than Zen4 (similar to on EPYC “Milan” sequence). The I/O die is smaller as nicely, round 397 mm² in comparison with 416 mm² on Zen3 EPYC CPUs. That stated, AMD had no hassle becoming 6 chiplets on all sides of the I/O die, contemplating that the SP5 (LGA 6096) package deal can be 37% greater than SP3.
AMD 16-core EPYC Genoa processor, Supply: VideoCardz
AMD’s new SP5 platform will assist as much as 12-channel DDR5 reminiscence as nicely PCIe Gen5 interface. AMD Genoa is already delivery to first clients, in keeping with AMD. The brand new EPYC 7004 sequence are actually on monitor to launch by the tip of this 12 months.
RUMORED AMD EPYC Processor Sequence Specs | ||||||
---|---|---|---|---|---|---|
VideoCardz | 7001 “Naples” | 7002 “Rome” | 7003 “Milan” 7003 “Milan-X” (*) |
7004 “Genoa” | 7004 “Bergamo” | 7005 “Turin” |
Launch | 2017 | 2019 | 2021 | 2022 | 2022 | 2023/2024 |
Structure | 14nm Zen | 7nm Zen2 | 7nm Zen3 | 5nm Zen4 | 5nm Zen4c | Zen5 |
Socket | SP3 (LGA4094) | SP3 (LGA4094) | SP3 (LGA4094) | SP5 (LGA-6096) | SP5 (LGA-6096) | SP5 (LGA-6096) |
Modules/Chiplets | 4xCCD | 8xCCD + 1xIOD | 8xCCD + 1xIOD | 12xCCD + 1xIOD | 12xCCD + 1xIOD | TBC |
Max Cores | ||||||
Max Clock | TBC | TBC | TBC | |||
L2 Cache Per Core | 0.5 MB | 0.5 MB | 0.5 MB | 1 MB | TBC | TBC |
L3 Cache Per CCX | 8 MB | 8 MB | 32 MB / 96 MB (*) | 32 MB | TBC | TBC |
Reminiscence Channels | ||||||
Reminiscence Assist | ||||||
PCIe Lanes | TBC | TBC | ||||
Max cTDP | TBC |
Supply: zhangzhonghao @ Chiphell by way of @9550pro
[ad_2]
Source link